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[Multimedia programCable Decoder 4.5 with FULL source.zip

Description: 电视解码
Platform: | Size: 381228 | Author: | Hits:

[Multimedia programCable Decoder 4.5

Description: 电视解码
Platform: | Size: 381952 | Author: 站长 | Hits:

[SCMhf.c

Description: 汽车电子解码器电缆测试。可以判断汽车故障在哪里-Automotive electronics testing cable decoder. Can determine where the fault automobile
Platform: | Size: 463872 | Author: 曾明 | Hits:

[File FormatSTI7105

Description: The STi7105 uses state of the art process technology to provide an ultra low-cost, fully featured HD AVC decoder IC. It is a highly integrated system-on-chip suitable for STB markets across all networks (cable/satellite/DTT/x- DSL/IP) worldwide-STI7105
Platform: | Size: 120832 | Author: 猫咪 | Hits:

[Documentsshuzi

Description: 设计一个采用数字电路实现,对时,分,秒.数字显示的计时装置,周期为24小时,显示满刻度为23时59分59秒,并具有校时功能和报时功能的数字电子钟。电路主要采用中规模集成电路.本系统的设计电路由脉冲逻辑电路模块、时钟脉冲模块、时钟译码显示电路模块、整电报时模块、校时模块等部分组成。采用电池作电源,采用低功耗的芯片及液晶显示器,发生器使用石英晶振、计数振荡器CD4060及双D触发器74LS74,计数器采用同步双十进制计数器74LS160,锁存译码器是74LS248,整电报时电路用74LS74,74LS32及扬声器构成。-Design a digital circuit, on the hours, minutes, seconds. Figures show that the timing device, 24-hour period, indicating full scale is 23:59:59 and the time with school functions and timekeeping functions of digital electronic clock. Scale integrated circuits used in the main circuit. The design of this system by the pulse logic circuit module, clock module, the clock display circuit decoding module, when the entire cable module, the campus module components. Using a battery powered, low-power chips and liquid crystal display generator using a quartz crystal oscillator, count of CD4060 oscillator and two D flip-flop 74LS74, two-decimal counter synchronous counter 74LS160, latch decoder is the 74LS248, the whole When telegraph circuits 74LS74, 74LS32 and loudspeaker
Platform: | Size: 449536 | Author: 张龙 | Hits:

[SCMc

Description: 动态显示-译码器片选实现 连接方法 :JP10 (P0)与J12 用8PIN排线连接-Dynamic display- to achieve the decoder chip select connection method: JP10 (P0) and the J12 cable connection with 8PIN
Platform: | Size: 110592 | Author: kaka | Hits:

[VHDL-FPGA-Verilogxapp288_SDI-decoder

Description: the document is related to video transmission and serial digirtal interface (SDI) standard which describes how to transport standard-definition digital video serially over coax cable
Platform: | Size: 107520 | Author: geunie | Hits:

[androiddtmf-decoder

Description: 一个DTMF的解码源代码,可以直接运行在Android 1.6以上的版本上,如果需要测试效果需要利用两根带MIC的耳机线做成两端3.5MM音频口直连,发射端直接用手机拨号即可看到另一端能解出相应的按钮-A DTMF decoder source code, can be directly run on Android 1.6 or later on, if the need to test the effect of two with MIC headphone cable made both ends 3.5MM audio port directly connected, the transmitter directly using a mobile phone to dial see the other end of the solution corresponding button
Platform: | Size: 684032 | Author: wuzuokun | Hits:

[VHDL-FPGA-Verilogshaomiaoqudongxianshidianlu

Description: 为了减少8位显示信号的接口连接线,实验箱中的数码显示采用扫描 显示工作模式。即8位数码管的七段译码输入(a,b,c,d,e,f,g)是并联在 一起的,而每一个数码管是通过一个3位选择sel[2..0]来选定 的。-In order to reduce the 8-bit display signal interface cable, digital display in the experimental box scan display mode of operation. I.e. the seven segment decoder 8-bit digital input (a, b, c, d, e, f, g) is connected in parallel with each digital tube is selected by a 3-bit SEL [2 .. 0] to be selected.
Platform: | Size: 1024 | Author: 刘红喜 | Hits:

[CSharpdsw

Description: P0与J12 用8PIN排线连接, P1与JP16 用排线连接,573锁存器控制和单片机脚直接位选控制(非译码器控制)数码管。-P0 and J12 cable to connect with 8PIN, P1 and JP16 with a ribbon cable, 573 feet latch control and chip select control bits directly (non-decoder control) digital tube.
Platform: | Size: 1024 | Author: 肖康 | Hits: